Issues

• [arch] ADR-001 also needs DDR3L clarification on top of bandwidth amendment (Stays #28)

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  popsolutions/MAST#33 · Filter by author marcos-mendez opened on May 6, 2026

• [arch] Amend ADR-001 — DDR3 bandwidth claim 12.8 GB/s is theoretical, real is 1.5-2.4 GB/s on ECP5+open toolchain

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  popsolutions/MAST#32 · Filter by author marcos-mendez opened on May 6, 2026
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• [cross-stream] interconnect block port surface must match InnerJib7EA intercard_link stub

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  popsolutions/MAST#29 · Filter by author marcos-mendez opened on May 6, 2026

• [arch] Decide whether contr_rd_data should also be wire (asymmetry with core1_rd_data)

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  popsolutions/MAST#28 · Filter by author marcos-mendez opened on May 6, 2026

• [hw] Re-verify single-deep contr_rd_pending latch when gpu_controller.sv migrates

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  popsolutions/MAST#21 · Filter by author marcos-mendez opened on May 6, 2026

• [hw] Delete src/global_mem_controller.sv when gpu_die.sv migrates to direct AXI4 adapter (PR-2b)

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  popsolutions/MAST#20 · Filter by author marcos-mendez opened on May 6, 2026

• [cross-stream] inter-card link bandwidth + latency model for scheduler

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  popsolutions/MAST#18 · Filter by author marcos-mendez opened on May 6, 2026

• [cross-stream] expose queryable axi4_mem_model state for ggml-spanker integration tests

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  popsolutions/MAST#17 · Filter by author marcos-mendez opened on May 6, 2026

• [cross-stream] LitePCIe has no ECP5 PHY — rev-A host-link path is unsupported upstream

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  popsolutions/MAST#13 · Filter by author marcos-mendez opened on May 6, 2026
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• [meta] Operating model 4+1 active — Sprint 7EA-W1 kickoff

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  popsolutions/MAST#11 · Filter by author marcos-mendez opened on May 6, 2026
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• [arch] ADR-014 — Inter-card link architecture choice (multi-card parallelism)

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  popsolutions/MAST#9 · Filter by author marcos-mendez opened on May 5, 2026
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